The present invention relates generally to memory systems and in particular, to flash memory array systems and methods for producing a voltage boost circuit, wherein a voltage detection circuit may be used to measure the VCC applied to a voltage boost circuit, along with boost compensation circuitry to regulate the boost voltage output from VCC variations. The boost voltage may be applied to a wordline for read mode operations of memory cells.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 1MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell associated with a given bit line has its stacked gate terminal coupled to a different word line, while all the flash cells in the array have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing); reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is the bit line, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between 0.5 and 1.0 volts in a read operation. A voltage is then applied to the gate (e.g., the word line) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (VT) and an unprogrammed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
More recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The bit line voltage required to read dual bit memory cells is typically higher than that of single bit, stacked gate architecture memory cells, due to the physical construction of the dual bit cell. For example, some dual bit memory cell architectures require between 1.5 and 2.0 volts to properly bias the bit line or drain of such cells in a read operation. Because the voltage applied to the bit line or drain of the memory cell is derived from the memory device supply voltage (VCC), the ability to provide the higher bit line voltage required to read the newer dual bit memory cells may be impaired when the supply voltage is at or near lower rated levels. In addition, low power applications for memory devices, such as cellular telephones, laptop computers, and the like, may further reduce the supply voltage available.
In a prior art flash memory device, boosted voltage circuits apply a boosted word line voltage for the read mode operations of memory cells. VCC variations are typically reflected in the output of the boost voltage circuit that is supplied to the word line of the flash memory array, during a read operation. Such variations in word line voltages from the boost circuit degrades the ability in the read mode circuitry to discriminate accurately whether or not a cell is programmed. In addition, as device densities and memory speed requirements continue to increase, the speed requirement of the voltage booster circuit may need to increase to keep pace with the remainder of the memory circuit. Further, as supply voltage levels decrease with the higher density architectures, a single stage voltage booster circuit may be inadequate to supply the required boost voltage. Accordingly, there is a need for a means of compensation for the variations in the VCC supply applied to a multi-stage boosted voltage circuit, and for fast boost voltage regulation.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
In the present invention of flash memory array systems and methods for producing a multi-stage voltage boost circuit, one or more output signals from a voltage detection circuit used to measure the value of VCC is applied to a voltage boost circuit that is used to generate a boosted word line voltage for the read mode operations of memory cells. VCC variations are typically reflected in the output of the boost voltage circuit that is supplied to the word line of the flash memory array. By compensating for the variations in the VCC supply applied to the voltage boost circuit, the boost voltage is regulated, thereby enabling a more consistent read voltage on the word line.
According to one aspect of the present invention, a voltage value associated with the VCC supply voltage is ascertained, for example, using an A/D converter. The determined voltage value is then used to compensate or otherwise adjust a single or a multi-stage voltage boost circuit. For example, a digital word representing the VCC voltage value is used to vary effective boost capacitance and load capacitance values within the voltage boost circuit, thereby resulting in an output boost voltage that is substantially independent of variations in VCC. Consequently, the present invention provides a generally constant boost voltage, for example, a boosted word line voltage, which facilitates an accurate reading of flash memory cells despite fluctuations in the VCC.
In another aspect of the present invention, the final regulated output voltage of the voltage boost circuit (voltage booster) is anticipated by selecting a set of predetermined boost cells to provide a boosted voltage level during a pre-boost timing preceding the boost timing. The pre-boost timing occurs before the A/D converter has completed determining and latching an output of the digital word representing the VCC voltage that is then followed by the actual boost operation during the boost timing.
In still another aspect of the present invention, the voltage booster circuit comprises a plurality of boost cells having one or more boost stage capacitors in each boost cell, a precharge circuit, and a timing control circuit comprising a precharge gate booster and a boost timer.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.